Optimal CMOS buffer taper

From: John Conover <john@email.johncon.com>
Subject: Optimal CMOS buffer taper
Date: Fri, 1 Apr 1994 18:45:05 -0800 (PST)

Hi Rick. In the February 1994 "IEEE Journal of Solid-State Circuits,"
volume 29, Number 2 (eg., the latest "red rag,") on pp. 155 is some
diatribe (referencing a previous submission,) on the optimization of
CMOS transistor W/L's for circuit speed.

_If_ it would be possible to incorporate the concepts of the above
optimization into a synthesis algorithm, one could make a statement
(assuming the synthesis heuristics were a very good approximation of
the min terms) that, "with a given semi-conductor technology, it would
be virtually impossible to design a smaller circuit that would go
faster, ie., the speed/size ratio of the synthesized circuit would be
optimal." Note that this would be true for ALL paths (not only those
specified as "critical,", and the circuit would be a prototype-if you
ignore enough things-ie., doubling the circuit size, would almost
double the circuit's speed.)

I don't know what dumping another variable into the path delay
calculations of a synthesis algorithm would do to the "approximate
solution" (ie., S. Annealing, or whatever,) mechanism-it might be
prone to getting stuck in a multi-dimensional local minima... I don't
know ... or maybe some of the newer genetic algorithms may be
applicable sense they are more robust in these scenarios.

Anyhow, it was just a crazy idea that I thought about when I read the
article-since a lot of folks are whining about the size and speed of
synthesized circuits-re: the DEC Alpha presentation of last year.



John Conover, john@email.johncon.com, http://www.johncon.com/

Copyright © 1994 John Conover, john@email.johncon.com. All Rights Reserved.
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