From: John Conover <>
Subject: Re: IBM
Date: Mon, 20 Feb 95 01:19 PST

Clif Schieck writes:

 > John,

 > It is not clear to me how the university connection can help CADmazing
 > answer these questions for IBM:

It is because the problem requires a system-theoretic solution. The
only people in the world working on this are the US Universities,
sponsored by DARPA, on behalf of their clients. (Don't forget that the
methodology that your customers currently use, VHSIC I an II, was
sponsered by DARPA to do up to 50K gate designs.)  The IBM EDA
software capability must address a design complexity of at least 10
million equivalent gates. Bear in mind that 90% of Cadence's customers
do less than 50K gate designs, and design complexity goes up with the
square, (and possibly exponentially,) of the number of gates, eg.,
although the complexity of the IBM developments are only 200X the
number of gates that Cadence optimizes their software for, the design
complexity is 40,000X. Cadence and Mentor optimize their software
around doing 40K gate designs, (because that is where the current
volume market is,) and, although the software has been used for 250K
gate designs, it is not efficient, nor is it reliable, nor does it
produce verifiable or reliable designs. The design methodology must
change at approximately 100K gate design complexity, to a concurrent,
distributed design environment, (which is a general engineering
methodology developed in the aerospace industry about 50 years ago.)
The IEEE published a position paper in 1991, that among other things
states that it is not appropriate to use behavioral level synthesis,
nor behavioral level simulation for verification. It was published in
the January 1991 "IEEE Journal of Solid-State Circuits," and outlines
the "state of the art" in EDA software. Most of the following is
related to that document. Among EDA professionals, the Cadence and
Mentor commercial software offerings are regarded as "entry level
systems," that will work without a lot of support, nor expense.

Cadence and Mentor's software is not compatible with distributed
methodologies, (eg., there is no inherent concurrency control, nor is
there any provision for parallelization or distributed processing, nor
is there a homogenous, portable, extensible database facility.)  The
following is a list of base requirements, (most of which IBM already
has,) and unless you are infinitely familiar with the concepts, I
would not recommend discussing them with any of the design methodology
or EDA software staff from Raleigh-most of these folks have developed
similar systems in the past, as has the EDA staff at DEC and
Intel. The attached list provides only a base foundation, and does not
elaborate on the more significant details of the architecture of
concurrent engineering environments.

These are only the requirements for the base foundation to an EDA
system, and does not address any point tools, or layout tools.  Those
are relatively easy, (if they were designed to operate in a
distributed environment.) It also does not address any manufacturing
issues, including diagnostics, test methodology, or fault
analysis. Note that only 5% of the software effort in a microprocessor
EDA development group is directed at design development activities-95%
is addressed to manufacturing issues. Also, note that the design
effort is only 15% of the engineering effort, with test methodologies,
diagnostics, process development, etc., taking the remaining 85%. In
point of fact, Intel has published that only 3% of the cost of putting
a processor into the market is design/development cost.

The following was cut from something I wrote for a client-it is
copyright, so although you can use it, it can not be copied, or given
to anyone outside of Cadmazing, without my permission. (I charge for
this stuff, and it never ceases to amaze me that people will pay money
for it-when the field is so well documented.) References are attached.

Base foundation issues:

    I) Distributed computing environment:

        A) Required for concurrent engineering methodology, which is
        the only known development methodology that will yield a
        reasonable chance of success at this level of design

        B) Probably requiring 50 to 100 workstations, in hierarchical
        network configuration. The network must be fiber-optic, and
        capable of at least 100 Mbits per second. The work stations
        should have 128Mbyte of core, and 4Gbyte of rotating memory
        each. The system engineering staff will be, approximately, one
        system engineer and one system administrator for each 10 to 25
        work stations. This does not include the software or library
        support staff.

        C) Auto-replication of the database, in a geographically
        disperse environment is mandatory-there is no way to backup a
        distributed environment.

        D) There is no commercially available EDA software that will
        work in a distributed, concurrent environment, so all EDA
        software will have to be developed through joint technology
        relationships, or developed internally.

    II) Homogenous, network wide, distributed EDA database:

        A) Probably object oriented, with inheritance of views.

        B) Full network wide, distributed, concurrency control, which
        is difficult since the formal theory of concurrency control in
        distributed databases is only several years old

        C) Full serialization control of transactions, which is
        difficult since the formal theory of transaction serialization
        is only a decade old.

        D) Commercial concurrent, distributed databases have
        inadequate performance for the EDA environment-most have
        algorithms that break database transactions into atomic
        functions that exhibit NP characteristics.

        E) There is no commercially available EDA database management
        systems that will work in a distributed, concurrent
        environment, so all EDA databases will have to be developed
        through joint technology relationships, or developed

    III) Design state transition generation program:

        A) Written in portable language, probably "C", but perhaps
        C++. This will be ported to the system and used as a
        verification and diagnostics tool for the design prototypes.

        B) Central to the simulation and verification
        methodology-without this, there is no practical way to
        simulate a design of this complexity.

        C) Required since approximately 100 million vectors will have
        to be simulated, and verified.

        D) There is no commercially available EDA state transition
        software that is available, so all EDA state transition
        software will have to be developed through joint technology
        relationships, or developed internally.

    IV) Distributed simulation:

        A) Simulation of 100 million vectors of a 10 million gates.

        B) Simulation done concurrently in approximately 250

        C) There are two possible distributed simulation strategies:

            i) Totally hierarchical, which is the preferred.

            ii) Dividing the simulation, temporally, into sections,
            simulating each section in the distributed environment,
            and comparing the state transitions to the output of the
            state transition generation program, which is the
            conventional methodology. It is doubtful if this
            methodology is applicable to super-scalar designs that are
            capable of executing multiple instructions per clock

        D) Probably at least switch level-no gate level or behavior
        level simulations would be permitted. This requirement is for
        super-scalar designs that are capable of executing multiple
        instructions per clock cycle.

        E) There is no commercially available EDA switch level,
        distributed simulation software that is available, so all EDA
        switch level, distributed simulation software will have to be
        developed through joint technology relationships, or developed


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John Conover,,

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