The concepts of Spatial Distortion Reduction Headphone Amplifier, and Direct Coupled Stereo Headphone Amplifier, were combined in the tape archive, DCSDRamplifier.tar.gz, which contains the simulations and printed circuit board, (PCB,) development database, (including industry standard Gerber format files, connectivity "rat nests", component vendor and bill of materials, cost estimates, etc.,) for the design of a high quality headphone amplifier, suitable for studio and broadcast applications.

The headphone amplifier uses two Lenovo/IBM laptop "bricks" wired in series to produce +/- 20V DC @ 4.5A, (available non-OEM on eBay for under $10 US, each, 50K hours MTBF,) which is reduced to +/- 15 V DC with on-board regulators, (LM7815 and LM7915, which will not be discussed here.)

References:

• "Improved Headphone Listening - Build a stereo-crossfeed circuit," Siegfried Linkwitz, December, 1971, Audio magazine.

• "Will Ambi-Sound Shatter the Peace and Quiet of the Stereo Market," Adrian Hope, New Scientist Jan 29, 1976.

• "The Physical and Psychophysical Basis of Sound Localization," Simon Carlile, 1996, (particularly, Figure 2.4.)

• "A Computer Model of Binaural Localization for Stereo-Imaging Measurement," Ewan A. Macpherson, October 1, 1989, Audio Engineering Society Convention 87, 1989, JAES Volume 39 Issue 9 pp. 604-622, September 1991.

The latter being the most influential, recommending a crossfeed between stereo channels with the following characteristics:

• Pole:

  • ~ 700 Hz.
  • LF crossfeed, f << 700 Hz. = -3 dB = 0.707 X
  • HF crossfeed, f >> 700 Hz. = -10 dB = 0.316 X

• Delay:

  • ~ 300 uS.
  • f << 700 Hz.

The Headphone Amplifier Crossfeed

The pole is implemented as a low frequency operational amplifier shelf filter circuit.

The delay is implemented as an operational amplifier all pass filter.

Figure I, (1600X1200,) is the schematic of the signal conditioning circuit for one channel of the the headphone amplifier. (The other channel is identical, except the component reference descriptors are changed to 5XX via a sed(1) script in the ~/Makefile.) The crossfeed from the other channel is BCFlf and BCFhf, (summed in U404, for the low frequency, and, high frequency, respectively,) and, to the other channel, ACFlf and ACFhf, (summed in U504, for the low frequency, and, high frequency, respectively.)

The design is a literal translation, (and circuit reductions will be left to the reader,) of the specification, with the following ancillary functions, (which are straight forward, and will not be discussed):

• U401 is a unity gain buffer to provide low frequency, (~ 5 Hz.,) role off to prevent saturation of the power amplifier DC servo loop, (see the power amplifier section for requirements.)

• U402 is a signal inverter with a gain of minus unity for summing one channel with the crossfeed of the other, (U404.)

• U403 is the low pass filter, ~ 700 Hz., for the crossfeed to the other channel, representing sound frequencies less than the diffraction frequencies around the human head.

• U406 is the high pass filter, ~ 700 Hz., for the crossfeed to the other channel, representing sound diffraction frequencies around the human head.

The 300uS delay, (representing the transient time of sound around the human head-from one channel to the other for frequencies < 700 Hz.,) is implemented as an all pass filter, U405. (In Spatial Distortion Reduction Headphone Amplifier, Addendum, it was implemented as a ring buffer in software.)

References:

• "An accurate analog delay circuit," Contributing Author, Electronic Design, Dec 1, 1997.

• "Group delay and phase delay".

In a linear phase system (with non-inverting gain), both tg and tphi are constant (i.e. independent of w,) and equal, and their common value equals the overall delay of the system.

The Laplace transform of an ideal delay is exponential:

          Vo / Vi = exp (-t * S)

        

(where t is the desired delay,) which requires an infinite number of poles and zeros to implement: we need an approximation. An accurate, simple approximation, to the ideal can be achieved by a technique known as Pade approximation. The first-order Pade approximation to an ideal delay has the following form:

          Vo / Vi = (1 - tS / 2) / (1 + tS / 2)

        

(where t is the desired delay.)

The all pass filter circuit has the following transfer function, which has the same form as the first order Pade approximation, with the R * C constant equaling half the desired delay time, t.

          Vo / Vi = (1 - RCS) / (1 + RCS)

        

The Headphone Power Amplifier

Figure II, (1600X1200,) is the schematic of the DC coupled power amplifier section of one channel of the headphone amplifier. (The other channel is identical, except the component reference designators are changed to 3XX via a sed(1) script in the ~/Makefile.)

The headphone amplifier produces a maximum continuous sound level intensity of 100 dB SPL, corresponding to 0 dBFS, consistent with OSHA 1910.95 for sound workers, which is a program level of 85 dB SPL, consistent with IEC 61938, (formerly IEC 268-15,) specifying that headphones will be driven from a 120 Ohm source impedance and a source level of 5 V RMS, maximum, (regardless of headphone impedance.) 5 V RMS probably corresponds to 0 dBFS, which is 100 dB SPL, (or 103 dB SPL, depending on the interpretation of EBU R68-2000 and/or EBU R89-1997.) An input voltage of 0.775 V RMS = 0 dbm should correspond to -15 dBFS = 85 dB SPL, the program level, to within a 6 dB pad for consistency with the other standards, 0 dBm and 0 dBV.

There are 5 low frequency poles in the openloop transfer function:

1. The dominant pole of U201, NE5534.

2. The dominant pole of U1, LT1151.

3. The pole determined by R207 and C202, S = -1 / (R207 * C202)

4. The pole determined by R209, R210 and C204, S ~ -(1 / ((R209||R210) * C204)

5. The pole determined by R208 and C203, S = 0 for an idealized U1, LT1151

There are 2 low frequency zeros in the openloop transfer function:

1. The zero determined by R208 and C203, S = -1 / (R208 * C203); this zero is canceled by the pole determined by R207 and and C202

2. The zero, fz, where the output of the integrator circuit, U1, LT1151, is less than the ratio R204 / (R204 + R203):

   • By superposition, fz is when Vo (R204 / (R204 + R203) = Vo (1 / (S (R208 * C203))) * (R203||R204 / ((R203||R204) + R209 + R210)), which calculates to 0.0420 Hz.

   • For unconditional low frequency stability, this zero, fz, must be less than:
     
     

     1. The dominant pole of U201, NE5534.

     2. The dominant pole of U1, LT1151.

     worst case, (W.C.,) over make and temperature. Unfortunately, the values of the two dominant pole frequencies are not guaranteed parameters, (the dominant poles will minimize, i.e., be W.C. at minimum temperature, maximum open loop gain, and, minimum GBW product, and are "typically," about 2.5 Hz.) The prudent judgment is for fz to be about two orders of magnitude less than either U201's, NE5534, or U1's, LT1151, "typical" dominant pole frequency.

     Additionally, the pole determined by R209, R210, and C204 must be greater than the fz zero frequency, (it calculates to 17 Hz., about an order of magnitude greater than either U201's and U1's "typical" dominant pole frequency.

See, also: "../dcservo" and "../dcserver/openloop" in the tape archive, DCSDRamplifier.tar.gz, for the closed and openloop gains, respectively, of the DC servo circuit.

As a demonstration, altering the value of C203 to 0.1uF, (i.e., decreasing by two orders of magnitude,) results in marginal stability, and further decreasing the value of C203 to 0.01uF results in an unstable, oscillatory, condition.

Note that U201, NE5534, is compensated for unity gain stability, (C201,) and has a dominant pole that is substantially higher than other operational amplifiers, (~ 100 Hz.,) with an open loop unity gain frequency of about 8.6 MHz., which is about an order of magnitude less than U202, LT1206, (which is configured for unity gain, and a bandwidth of about 66 MHz., e.g., the high frequency open loop characteristics of the circuit is dominated by the open loop characteristics of U201, NE5534.) U201, NE5534, is stable with C201 = 0pf for closed loop gains greater than 3. The full power bandwidth of U201, NE5534, is about 70 KHz, (adequate for audio,) and the negative unity gain configuration is unconditionally stable.

Additionally, the zero, fz, where the output of the integrator circuit, U1, LT1151, is less than the dominant pole of U201, NE5534, by about 2 orders of magnitude.

Note that the circuit can correct a maximum Vos, (i.e., Vo with Vi = 0 V DC,) of (13 * (R203||R204)) / ((R203||R204) + R209 + R210) Volts, or about +/- 171 mV DC; the Vos, and contributions of Ios of U201, and, any DC input voltage from preceding stages, must be less than 171 mV, DC:

• Vos < 10 uV at 25C

• Vos < 12 uV 0 to 41 C, (32 to 105 F,) W.C.

Note that the input signal low frequency bandwidth must be restricted, (~ 1.0 Hz., minimum, 20 dB / decade, minimum,) to prevent U1, LT1151, from saturating at about +/- 12 V peak output voltage; see: ./sigcona.sch, above.

Additionally, the output signal of U1, LT1151, must not exceed 10 V RMS, (Vo = Vi = 5 V RMS = 0 dBFS,) over any frequency, make, temperature, etc., worst case, (W.C.) A safety factor of about 2 would seem prudent, (i.e., Vi = 5 * sqrt (2) * 2 ~ 14; 14 / sqrt (2) = 10 V RMS, which is near the +/- 12 V peak output voltage,) which defines the product of R401 and C401 in ./sigcona.sch, above.

Power considerations, U202, LT1206:

• Assume driving the output short circuited to ground, for worst case, (W.C.,) design; the resistance is 120 Ohms, which is driven to 5 V RMS, (which corresponds to 100 dB SPL, 0dBFS):
  
  

  • Po = 5^2 / 120 = 0.208 W

  • Pd, (assuming 5 V rails, square wave or DC output,) = Po

  • Io = 5 / 120 = 41.7 mA RMS

  • Pd, (assuming 15 V rails,) = 0.208 + (15 - 5) * 0.0417 = 0.625 W

• The maximum ratings for the LT1206, DIP8, is Tj-A = 100 C/W, Tjmax = 150 C, TAmax = 85 C.
  
  

  • 85 C + (0.625 * 100) = Tj = 147.5 C ~ 150 C.

  • 85 C TA is the limiting value, (inside the enclosure, W.C., a shorted output, at Vo = 5 V, corresponding to 100 dB SPL, 0dBFS, square wave or DC signal.)

  • For a maximum ambient temperature of 70 C, (consumer "standard,") the temperature rise inside the enclosure is 15 C. Assuming 2 devices in the enclosure, each dissipating 0.625 W = 1.25 W, a heat sink of 15 / 1.25 = 12 C / W is required.

  • sqrt (a) * C / W = 20, a = square inches, for single sided convection aluminum sheet.
    
    

    • 50 / sqrt (A), A = cm^2, = C / W = 12

    • sqrt (A) = 50 / 12 = 4.2 cm X 4.2 cm

    • A = 17.4 cm^2

which is the minimum enclosure size for TA = 70 C, W.C., where the enclosure, (at least 1.7" X 1.7" in size, almost a given with a circuit of this size,) dissipates the heat generated by both LT1206 power amplifiers.

PC Board

The PC board is dual layer, (top and bottom, only,) and uses a minimum of 20 mil line widths and 20 mil spacing, (common in linear designs,) which can be manufactured economically at almost any vendor of choice. The boards are designed to be mounted flat, (with 4 fasteners, one in each corner.)

The power supplies for the headphone amplifier are two Lenovo/IBM laptop "bricks" wired in series to produce +/- 20V DC @ 4.5A, (available non-OEM on eBay for under $10 US, each, 50K hours MTBF.) The PC board contains +/- 15V regulators, and separate power and signal grounds. The signal path(s) use 275V polypropylene capacitors-a substantial cost reduction can be obtained by relaxing this requirement, (the requirement is the prevailing wisdom in the industry.) The signal path parametrics can be altered, (usually,) with only resistor changes on the PC board-the capacitor values chosen are in the center of the applicable range. The signal conditioning paths use NE5534 Low-Noise High-Speed Audio Operational Amplifiers, (and the designs are compatible with the LT1115 Ultra-Low Noise, Low Distortion, Audio Op Amp, as a direct replacement.) All components are through hole, and SMT components are available.

The tape archive, DCSDRamplifier.tar.gz, contains the simulations and printed circuit board, (PCB,) development database, (including industry standard Gerber format files, connectivity "rat nests", component vendor and bill of materials, cost estimates, etc.,) to reproduce, enhance, or modify the circuits used in the headphone amplifier. The design environment used is gEDA. The development system uses gEDA Electronic Design Automation tools, particularly, Gschem(1), for schematic capture and Spice electronic circuit simulation netlist extraction. Ngspice was used for the Spice circuit simulations. RCS was used for version control in the development.

The PC board was designed using PC Board Circuit Editor from the gEDA suite.

Figure III is a plot of the stereo headphone signal conditioning and power amplifier printed circuit board, (both channels,) measuring 7.0" X 6.0", and component BOM, DCSDRA.bom.

License

A license is hereby granted to reproduce this software for personal, non-commercial use.

THIS PROGRAM IS PROVIDED "AS IS". THE AUTHOR PROVIDES NO WARRANTIES WHATSOEVER, EXPRESSED OR IMPLIED, INCLUDING WARRANTIES OF MERCHANTABILITY, TITLE, OR FITNESS FOR ANY PARTICULAR PURPOSE. THE AUTHOR DOES NOT WARRANT THAT USE OF THIS PROGRAM DOES NOT INFRINGE THE INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY IN ANY COUNTRY.

So there.

Copyright © 1992-2015, John Conover, All Rights Reserved.

Comments and/or problem reports should be addressed to:

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